NTL Record

Title Advanced computer architecture for large-scale real-time applications.
Record ID 38689
Personal Name
Creator
Wang, Gary Y.
Source 184p. in various pagings
Corporate Creator John A. Volpe National Transportation Systems Center (U.S.)
Publisher United States. Department of Transportation. Federal Aviation Administration
Publication Date 19730401
Language English
Abstract Air traffic control automation is identified as a crucial problem which provides a complex, real-time computer application environment. A novel computer architecture in the form of a pipeline associative processor is conceived to achieve greater performance improvement over the present air traffic control system by parallel processing. This new processor is structured into a multiprocessor configuration for reliability enhancement. Problems associated with multiprocessors are identified with special emphasis on execution time anomalies and memory conflict. A direct graph model is used for analysis from which simple heuristics are established for memory allocation and dynamic task scheduling to achieve optimal performance with minimal system overhead. These schemes are simulated and the results obtained follow closely the predicted system behavior. The report includes a discussion of the GASP II simulation programming language, and the FORTRAN H-516 simulation program listings for analysis of the proposed processor. (Author)
Rosap ID dot:9171
Rosap URL https://rosap.ntl.bts.gov/view/dot/9171
TRT Terms Air traffic control; Parallel processing; Real time data processing; Information processing
Geographical
Coverage
United States
Report Number DOT-TSC-FAA-72-21; FAA-RD-72-101
Availability Volpe National Transportation Systems Center, Technical Reference Center
Resource type Tech Report
URL https://ntlrepository.blob.core.windows.net/lib/38000/38600/38689/DOT-TSC-FAA-72-21.pdf
Format PDF
Database NTL Digital Repository